CS  441:  MODERN COMPUTER ARCHITECTURE
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                            Assignment #3
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                          Due date: 03/01/99



     1. The following code is to be run on a dynamically scheduled
        scoreboard-based processor. 

 
                   LD      F2,  0(R1)
                   ADDD    F0,  F2,   F4
                   MULTD   F6,  F8,   F10
                   SUBD    F12, F6,   F14
                   ADDD    F14, F16,  F0

 
           Assume that the machine has 
                - 1 integer unit (1 cycle execution time) 
                - 2 FP adders (4-stage pipelines)
                - 1 FP multiplier (12-stage pipeline)
 

        (a) Show the states of each of the instruction status, 
            functional unit status and register result status
            tables at the point when
             - the SUBD instruction is just ready to fetch its 
                                                  operands
             - the second ADDD instruction is just ready to 
                                     write back its result.
 
         (b) Prepare a matrix (rows correspond to instructions and
             columns to the stages - Issue, RO, etc.) where the
             i,j th entry indicates the precise cycle during which
             instruction i has advanced to stage j.


     2. Problem 4.11 (Chapter 4, p. 365) of text (H&P).
        Read the first paragraph on p. 276 carefully before attempting
        this question. (Given a base CPI of 1 ignoring unconditional
        branches, the CPI may actually decrease after considering
        the effect of unconditional branches assuming support for
        'branch folding' !)


     3. Problem 4.19 (Chapter 4, p. 368) of text (H&P).