Research Scholar |
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Currently working on Systems Design with Prof. Kavi Arya (KReSIT) and Prof. Madhav P. Desai (EE).
Current coding effort involves generating a hardware implementation out of simple C programs, with the aim of exploring issues in RTL generation and systems-level modeling and verification.
Tools used:
MTech from KReSIT
My MTech Project involved the design of an FPGA-based Reconfigurable Packet Classifier, intended for the network interface of a PC. This was carried out under the guidance of:
Presented a seminar on Hardware Compilation as part of the MTech course requirements.
BE Electronics from D. J. Sanghvi College of Engineering, Vile Parle, Mumbai (2001)
High School (12th Standard) from the B. N. Bandodkar College of Science, Thane (1997)
Received the National Talent Search (NTS) scholarship from NCERT (1995)
Secondary and Primary schooling at Sau. Anandibai Keshav Joshi English Medium School, Thane (1995)
-----BEGIN GEEK CODE BLOCK----- Version: 3.1 GIT d-@ s: a- C++>$ UL P++ L++ E W++ N+ o? K? w O? M-- V? PS+ PE++ Y+ PGP t+ 5? X+ R tv+@ b++>+++ DI+ D G e+++>++++ h--- r+++ y? ------END GEEK CODE BLOCK------And that means ...
| Last modified on Sunday, 4th January 2009 |