Research Scholar

Sameer D. Sahasrabuddhe K.R.School of Information Technology Department of Computer Science and Engineering, Indian Institute of Technology Bombay, Powai, Mumbai - 400 076. (India) Email: sameer@sbuddhe.net My blog.

Research Interests

• Systems Design
• Reconfigurable Computing
• Embedded Systems

Publications

• "Towards Software-defined Silicon: Applying LLVM to Simplifying Software" by Teemu Rinta-Aho, Adnan Ghani, Sameer D. Sahasrabuddhe and Pekka Nikander, presented at the 3rd Workshop on Infrastructures for Software/Hardware co-design (WISH 2011), April 2011.
• "A C-to-RTL flow as an energy efficient alternative to embedded processors in digital systems" by Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya and Madhav P. Desai, presented at the 13th Euromicro Conference on Digital System Design (DSD), September 2010
• "Towards Software-defined Silicon: Experiences in Compiling Click to NetFPGA" by Pekka Nikander, Benny Nyman, Teemu Rinta-aho, Sameer D. Sahasrabuddhe and James Kempf, presented at the 1st European NetFPGA Developers Workshop , September 2010
• "A competitive pathway from high-level programs to hardware specifications" by Sameer D. Sahasrabuddhe, PhD Thesis, Indian Institute of Technology Bombay, Powai, Mumbai, October 2009. (synopsis)
• "AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Languages" by Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya and Madhav P. Desai, presented at the 20th International Conference on VLSI Design, January 2007

Academics

• PhD Computer Science, Dept. of Computer Science and Engineering, IIT Bombay (October 2009)

  My PhD Thesis established a competitive flow from algorithms to hardware. We have implemented a high-level synthesis flow that translates algorithms expressed as programs to hardware descriptions. The flow is based on an intermediate representation that factorises the program into three aspects --- control, data and storage. The representation is independent of the programming language used and supports scalable optimisations. The resulting compiler flow produces hardware implementations that are correct by construction --- the behaviour of the hardware is provably equivalent to the original program.

  This work was carried out under the guidance of Prof. Kavi Arya and Prof. Madhav P. Desai.

• MTech IT, Kanwal Rekhi School of IT, IIT Bombay (December 2002)

  My MTech Project involved the design of an FPGA-based Reconfigurable Packet Classifier, intended for the network interface of a PC under the guidance of Prof. Kavi Arya and Prof. D. Manjunath.

• BE Electronics from D. J. Sanghvi College of Engineering, Vile Parle, Mumbai (2001)

• High School (12th Standard) from the B. N. Bandodkar College of Science, Thane (1997)

• Received the National Talent Search (NTS) scholarship from NCERT (1995)

• Secondary and Primary schooling at Sau. Anandibai Keshav Joshi English Medium School, Thane (1995)

Other stuff

• SIGFood
• An article on VLSI Design
• A pretty concise way to describe me:

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              ------END GEEK CODE BLOCK------
            

  And that means ...